The present invention relates to electrically erasable and programmable memories (EEPROMS), and in particular, to a EEPROM series memory (i.e., a memory with a series input/output or with a series input). The present invention more particularly relates to reading and storing in an EEPROM special bits, such as condition bits and configuration bits.
FIG. 1 represents a conventional series memory MEM1 comprising a memory array MA1 of electrically erasable and programmable memory cells CEL connected to word lines WLi and to bit lines BLj. The memory array MA1 comprises m word lines WL0 to WLmxe2x88x921 and n columns COL0 to COLnxe2x88x921, with each column comprising M bit lines BL0 to BLMxe2x88x921. Selection of the memory cells for reading or writing is carried out by a decoder WLDEC1 connected to the word lines WLi, and a decoder COLDEC1 connected to the bit lines. The writing of data is performed by programming latches LTB1 connected to the columns via the decoder COLDEC1, while the data is read by a reading circuit RC1. The circuit RC1 comprises M sense amplifiers SA0 to SAMxe2x88x921 enabling simultaneous reading of M memory cells belonging to a column selected by the decoder COLDEC1 and to a line selected by the decoder WLDEC1.
These diverse elements are driven by a sequencer SEQ1 connected by a data bus DTB to the outputs of the circuit RC1 and to the inputs of the latches LTB1. An address bus ABD connects these elements to the decoders COLDEC1 and WLDEC1. The sequencer SEQ1 is connected to terminals T1, T2, T3 and T4 for receiving or transmitting signals described below.
The memory MEM1 also comprises two registers STREG1 and CFREG1, which are volatile type registers. The register STREG1 contains special bits of a first type, for example, protection bits of the memory array. These bits are to be preserved outside the periods of utilization of the memory, and a special zone A1 is provided in the memory array to store them in a non-volatile fashion. The special zone A1 of the memory array is, for example, connected to an additional word line WLm added to the m word lines of the memory array.
The register CFREG1 contains special bits of a second type, for example, configuration bits acting on certain elements of the memory. This register is used by the manufacturer to set up the memory during a test and adjustment phase before marketing. The parameters that can be adjusted due to the configuration bits are quite varied and include the following: the level of a program erasing high voltage Vpp; the level of a gate control voltage during the reading phases; the number of current generators activated in the sense amplifiers; current adjustment in the current generators; and the durations of certain internal delays, for example.
Since the configuration bits may also be preserved when the memory is switched off, a special zone A2 is dedicated to them in the memory array. The zone A2 is, for example, connected to a second additional word line WLm+1.
Conventionally, the register STREG1 is read accessible and the memory zone A1 is write accessible by applying to the memory special instructions in the form of operating codes. The memory zone A2 is moreover read and write accessible by applying to the memory operating codes that are generally not communicated to the user and remain exclusive to the manufacturer. The user is not supposed to be aware of the existence of configuration bits.
Such a memory should be suitably equipped to read the zone A2 before performing a first instruction. This is because the configuration bits define the operation of the memory, and must be loaded into the register CFREG1 for the configuration to be effective before performing the first instruction. For reasons explained below, the zone A1 must also be read before performing a first instruction, and the condition bits must be loaded into the register STREG1.
With respect to FIGS. 2A to 2D, the execution of a first instruction after activation of the memory, for example, an instruction for reading the memory array, will now be considered. FIG. 2A represents a selection signal CS (chip select) applied to the terminal T1. FIG. 2B represents clock signals applied to the terminal T2. FIG. 2C represents data DTIN applied to the terminal T3. FIG. 2D represents data DTOUT delivered by the sequencer on the terminal T4, either data read in the memory array or in the registers. The signal CS is set to 0 to activate the memory and the clock signal CK is then applied to the terminal T2. As of the first clock cycle, data DTIN is applied to the terminal T3. This data comprises an operating code COP, containing generally 8 bits, such as a code relating to a reading operation, then address bits ADD.
After having received the operating code and the address bits, the sequencer SEQ1 can read the memory zone affected and deliver the data DTOUT. During the reception of the address bits, the sequencer has enough time to decode the operating code. However, if the first operating code received is an instruction for reading the register STREG1, this code is not provided with address bits. If it is expected that all the code bits are received to execute the instruction, i.e., in this case the eighth clock cycle, the content of the zone A1 must be read into the memory array, loaded in the register STREG1, then delivered to the terminal T4 within a very short time. This is typically equal to 0.5 or 1.5 clock cycles according to the series communication protocol used.
Reading the zone A1 before the execution of the first instruction enables the condition bits to be loaded into the register STREG1, and to deliver them on the series output of the memory if the first instruction received is an instruction for reading the register STREG1. Thus, the condition bits and the configuration bits must be read in the zones A1, A2 and loaded in their respective registers before the execution of a first instruction, i.e., during the reception of the first clock signals.
The time conferred upon the sequencer for both these successive reading operations corresponds in theory to eight clock cycles. The first clock cycles are necessary for the stabilization of reference circuits intervening in the reading of the memory array, and the effective time available to the sequencer is greatly reduced. This time is sufficient with slow clock frequencies, but is currently becoming critical due to the increase in the clock frequencies, notably with clock frequencies equal to or greater than 20 MHz.
In view of the foregoing background, the present invention is based upon the practical observation that the sum of the bits of the first type and of the second type is generally smaller than or equal to M, with M being the number of bit lines per column, so that M sense amplifiers provided in a memory to read the M memory cells of a selected column may be enabled to read simultaneously the condition bits and the configuration bits.
For example, diverse memories marketed by the current assignee of the present invention comprise 3 condition bits and 5 configuration bits. The three condition bits comprise a bit for write-protection of the memory array (bit Write Enable) and two additional bits forming a code determining the fraction of the write-enable memory array (25, 50, 75 or 100% of the memory array). The five configuration bits form a configuration code offering 25 possibilities for setting up a memory.
The present invention includes reading simultaneously the bits of the first type and of the second type. The bits of the first type and of the second type cannot be arranged on the same word line, since erasing bits of the first type would erase bits of the second type and vice-versa.
The present invention thus relates to enabling a simultaneously reading of at least two special zones in which are recorded special bits of two distinct types that cannot be erased simultaneously. To obtain this feature, the present invention also provides two special zones that are connected to two distinct word lines, but whose connections to bit lines are such that they enable a simultaneous reading of certain memory cells present in each of the zones.
More particularly, the present invention provides an electrically erasable and programmable memory comprising a memory array comprising memory cells connected to word lines and to bit lines, with the bit lines being arranged in columns. The memory array comprises at least a first special zone for storing special bits of a first type, and at least a second special zone for storing special bits of a second type.
The first special zone comprises at least a first row of memory cells connected to a first word line, wherein N1 memory cells are connected to N1 bit lines of at least a set column of the memory array comprising M bit lines. The second special zone comprises at least a second row of memory cells connected to a second word line, wherein N2 memory cells are connected to N2 other bit lines of the set column of the memory array. The N1 bit lines of the set column that are connected to the N1 memory cells of the first row are not connected to the memory cells of the second row, and the N2 bit lines of the set column that are connected to the N2 memory cells of the second row are not connected to memory cells of the first row.
According to one embodiment, N2=Mxe2x88x92N1. The first row may comprise M memory cells connected to the first word line, and the second row may comprise M memory cells connected to the second word line. The memory may also comprise means for simultaneously applying a reading voltage to the first and second rows of memory cells when reading special bits.
The memory may comprise at least M sense amplifiers for simultaneously reading N1 memory cells of the first row and N2 memory cells of the second row. The memory may further comprise a first register for temporary storage of the special bits of the first type read in the memory cells of the first row, and a second register for temporary storage of the special bits of the second type read in memory cells of the second row.
The memory may further comprise a sequencer to automatically trigger a simultaneous reading of special bits of the first and second types during the reception of first clock signals. The special bits of the first type may be condition bits whose value determines the write-accessibility of the memory array, in whole or in part. The special bits of the second type may be configuration bits whose value determines the hardware configuration of certain elements of the memory.
The present invention is also directed to a process for storing and reading special bits of a first type and of a second type in an electrically erasable and programmable memory. The memory comprises a memory array comprising memory cells connected to word lines and to bit lines, with the bit lines being arranged in columns.
The process comprises operations that provide in the memory array at least a first special zone comprising at least a first row of memory cells connected to at least a first word line, wherein N1 memory cells are connected to N1 bit lines of at least a set column of the memory array comprising M bit lines. At least a second special zone is provided in the memory array comprising at least a second row of memory cells connected to at least a second word line, wherein N2 memory cells are connected to N2 other bit lines of the set column of the memory array. The N1 bit lines of the set column that are connected to the N1 memory cells of the first row are not connected to memory cells of the second row, and the N2 bit lines of the set column that are connected to the N2 memory cells of the second row are not connected to memory cells of the first row.
According to one embodiment, N2=Mxe2x88x92N1. The first row may comprise M memory cells connected to the first word line, and the second row may comprise M memory cells connected to the second word line. Both rows of cells can be read simultaneously. The special bits of the first type may be condition bits whose value determines the write-accessibility of the memory array. The special bits of the second type may be configuration bits whose value determines the hardware configuration of certain elements of the memory.